PIC16F639-E/SS【PDF 35/74 页】IC MCU FLASH 2KX14 20SSOP

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Sheet目录3876

31页 32页 33页 34页 [35页]36页 37页 38页 39页

Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

MAC Multicast Table 1 Register (MTR1 Offset 0x0024)

The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the

CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the

Bit

Default

Read/

Write

Description

31-0

0x00000000

MTR0 Multicast Table 1

When appropriate bit is set, the packet received with DA matches the

CRC hashing function is received without being filtered.

Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in

the RXCR then all multicast addresses are received regardless of the

multicast table value.

Interrupt Enable Register (INTEN Offset 0x0028)

This register enables the interrupts from the internal or external sources.

The following table shows the register bit fields.

Bit

Default

Read/

Write

Description

DMLCIE DMA MAC Link Changed Interrupt Enable

When this bit is set, the DMA MAC Link Changed Interrupt is enabled.

When this bit is reset, the DMA MAC Link Changed Interrupt is

disabled.

DMTIE DMA MAC Transmit Interrupt Enable

When this bit is set, the DMA MAC Transmit Interrupt is enabled.

When this bit is reset, the DMA MAC Transmit Interrupt is disabled.

DMRIE DMA MAC Receive Interrupt Enable

When this bit is set, the DMA MAC Receive Interrupt is enabled.

When this bit is reset, the DMA MAC Receive Interrupt is disabled.

DMTBUIE DMA MAC Transmit Buffer Unavailable Interrupt Enable

When this bit is set, the DMA MAC Transmit Buffer Unavailable

Interrupt is enabled.

When this bit is reset, the DMA MAC Transmit Buffer Unavailable

Interrupt is disabled.

DMRBUIE DMA MAC Receive Buffer Unavailable Interrupt Enable

When this bit is set, the DMA MAC Receive Buffer Unavailable Interrupt

is enabled.

When this bit is reset, the DMA MAC Receive Buffer Unavailable

Interrupt is disabled.

DMTPSIE DMA MAC Transmit Process Stopped Interrupt Enable

When this bit is set, the DMA MAC Transmit Process Stopped Interrupt

is enabled.

When this bit is reset, the DMA MAC Transmit Process Stopped

Interrupt is disabled.

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